The present invention relates to an enabling circuit for output devices in electronic memories which allows updating of the data presented outside the memory in accordance with a memory architecture of the interleaved type.
It is known that in conventional electronic memories the output circuits are normally managed by a timing which is meant to activate a direct connection between the sense amplifier and the corresponding output stage.
This connection is usually continuous and maintained over time, but it can be of the sampled type when using output stages which are internally provided with a latch structure.
However, at the end of a read cycle there is always an updating of the output stage, and such updating is always the image of the data item produced by the sense amplifier.
Moreover, the circuits that oversee the generation of the control signals of the output stage have the sole purpose of ensuring the correct updating of the memory output buffer.
The problem of the tristate configuration that the memory can assume is particularly simple, and since it is independent of the actual moment when the output stage is updated, it is managed autonomously and immediately by two control signals which are provided for this task, i.e., OEn (Output Enable) and CEn (Chip Enable).
In memories having an architecture of the interleaved type, which are the subject of copending patent applications in the name of this same Applicant as the present application, the control circuits can no longer be considered as such in the conventional sense, and the particularities of the architecture of the memory lead to the need to find different approaches.
The aim of the present invention is to provide an enabling circuit for output devices in electronic memories to ensure a connection between the sense amplifier and the corresponding output buffer in more than one of the operating modes that the memory can assume.
Within the scope of this aim, an object of the present invention is to provide an enabling circuit for output devices in electronic memories to generate synchronization signals which are useful for synchronization of the timing activities of the memory.
Another object of the present invention is to provide an enabling circuit for output devices to stimulate the timing activities of the memory in accordance with the configuration of the control signals that are characteristic of the current operating mode of the memory.
Another object of the present invention is to provide an enabling circuit for output devices in electronic memories to present the data in output synchronously, asynchronously or in a deferred mode.
Another object of the present invention is to provide an enabling circuit for output devices in electronic memories in which the conditions allowing updating of the output devices are compatible with the interleaved protocol used in the memory.
Another object of the present invention is to provide an enabling circuit for output devices in electronic memories to disable, when required, the external visibility of the data read by the sense amplifier.
Another object of the present invention is to provide an enabling circuit for output devices in electronic memories to generate pulses whose duration is closely correlated to the propagation characteristics of the controlled networks, such as address increment circuits and the like.
Another object of the present invention is to provide an enabling circuit for output devices in electronic memories which allows in general management in a flexible manner the reading operations in the volatile and non-volatile memory.
Another object of the present invention is to provide an enabling circuit for output devices in electronic memories which provides visibility of the data by pulsed signals when a synchronous mode is chosen (interleaved function) or by continuous signals which are closely linked to the external control signals when a synchronous or conventional mode is chosen.
Another object of the present invention is to provide an enabling circuit for output devices in electronic memories which can produce the updating pulse promptly at each transition prescribed by the interleaved protocol.
Another object of the present invention is to provide an enabling circuit for output devices in electronic memories to preset the conditions of suitability for a new pulse exclusively following a verified lo condition of low level of the RD signal.
Another object of the present invention is to provide an enabling circuit for output devices in electronic memories which is capable of producing control signals adapted to prevent the memory from being sensitive to noise.
Another object of the present invention is to provide an enabling circuit for output devices in electronic memories which is highly reliable, relatively simple to manufacture and at competitive costs.
This aim, these objects and others which will become better apparent hereinafter are achieved by an enabling circuit for output devices in electronic memories, comprising:
means for driving the loading of an output buffer of an electronic memory;
output enabling means which are adapted to drive said output buffer loading driver means;
timer means which are adapted to control the switching of said output enabling means;
a stimulus signal for the loading of said output buffer, produced by switching means, on the basis of a read mode signal, which performs a switching, inside said switching means, between separate reading paths of said electronic memory.